Analog IC Layout Design Engineer
Location: Shanghai
Description:
1.Familiar with analog IC layout design flow.
2.Best performance with optimized layout design.
3.Complete layout physical verification.
4.Complete the Sign-off process and inspection, and write layout design documents.
Qualifications:
1.A college degree or a bachelor in Electrical Engineering with 3+ years of experience in analog IC layout design.
2.Cooperating and collaborating with Senior Analog Designer.
3.Be patient and careful reconsideration to optimize layout performances

 If you want to be considered for a position at Consonance, please send your resume to “info@consonance-elec.com”